tag:blogger.com,1999:blog-3155908228127841862.post5763905025208074819..comments2023-06-28T10:04:44.463-06:00Comments on The Perils of Parallel: Transactional Memory in Intel Haswell: The Good, and a Possible UglyGreg Pfisterhttp://www.blogger.com/profile/12651996181651540140noreply@blogger.comBlogger8125tag:blogger.com,1999:blog-3155908228127841862.post-14521124048843016342013-01-08T03:57:35.290-07:002013-01-08T03:57:35.290-07:002- why the lock-based solution need extra copy. in...2- why the lock-based solution need extra copy. in fact i suspect the transactional one to have extra copy. all you need is 20bit mask for marking what is locked and what not !?!?!?!?!?!?!pip010https://www.blogger.com/profile/01451646330176713157noreply@blogger.comtag:blogger.com,1999:blog-3155908228127841862.post-88761008537998066182012-09-02T02:42:39.117-06:002012-09-02T02:42:39.117-06:001. Reads outside locked region would show inconsis...1. Reads outside locked region would show inconsistent state before. I think the code that reads values outside "Transaction On!" is not guaranteed to NOT see B inconsistent with A. Too many nots? OK, only transactional code is required to see A and B consistent.<br /><br />2. If I wanted to modify 2 out of 20 fields in a object, the lock-based solution would need to create a copy of the object with the 2 fields modified by a single thread, then "swap-in" the mutated object. The big win of transactional memory is that now we don't need to create new objects to represent the whole state of the system anymore, we can mutate the state in place.Sassahttps://www.blogger.com/profile/13008666335582702807noreply@blogger.comtag:blogger.com,1999:blog-3155908228127841862.post-84123143231079946632012-03-19T16:12:21.379-06:002012-03-19T16:12:21.379-06:00I might be overlooking something obvious, but it s...I might be overlooking something obvious, but it seems to me that you could solve this problem with another state in your coherence protocol. There's no need for a pipeline flush -- anything already brought in from DRAM is still good to compute with, until it points to a memory location not yet brought into the processor, at which point it sees an invalidation and rolls out to the abort block. It seems that what you *can't* have is actual instruction retirement from a transactional region when another has acquired the xaction? Regardless, the cache coherence protocol -- as you note at the beginning -- ought provide most of the mechanics for this.nick blackhttps://www.blogger.com/profile/13939083300875476344noreply@blogger.comtag:blogger.com,1999:blog-3155908228127841862.post-50271420791137795582012-02-23T10:48:35.876-07:002012-02-23T10:48:35.876-07:00No sure why you assume that cache invalidates to t...No sure why you assume that cache invalidates to take ownership have to happen at "commit" as opposed to when the write happens. That might cause excessive serialization at release but is not neccessary.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-3155908228127841862.post-6379227747105736992012-02-18T18:41:37.140-07:002012-02-18T18:41:37.140-07:00BG/Q was designed to have only one chip per node, ...BG/Q was designed to have only one chip per node, so I don't see how it's a problem that TM only works in this context. Similarly, the question of cache coherence between multiple chips in a node is irrelevant because this configuration will never exist.Jeff Hammondhttp://www.linkedin.com/in/jeffhammondnoreply@blogger.comtag:blogger.com,1999:blog-3155908228127841862.post-90084813900958645052012-02-15T06:46:59.689-07:002012-02-15T06:46:59.689-07:00nice post, spectacular blognice post, spectacular blogAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-3155908228127841862.post-36284258707763736552012-02-14T20:45:32.649-07:002012-02-14T20:45:32.649-07:00BG/Q - I've not read any architecture document...BG/Q - I've not read any architecture documents on that, but my understanding is that it does, except that in BG/Q it's limited to working within a single chip, not across multiple chips in a node. This makes software exploitation more difficult. <br /><br />However, I'm not certain that BG/Q has cache coherence across the multiple chips in a node, so transactional memory across the chips wouldn't be as useful anyway.Greg Pfisterhttps://www.blogger.com/profile/12651996181651540140noreply@blogger.comtag:blogger.com,1999:blog-3155908228127841862.post-31928694557084768892012-02-14T20:11:58.566-07:002012-02-14T20:11:58.566-07:00Does this work the same way as the transactional m...Does this work the same way as the transactional memory on the IBM BG/Q processor ?Anonymousnoreply@blogger.com